As the design rule for fabricating semiconductors such as LSI has been dramatically reduced in the recent years, a variety of technologies in semiconductor design and manufacturing has been highly developed. On the other hand, the market always creates strong demand for fabricating cheaper, smaller, and lighter electronic products offering better performance and more functionality. The number of electronic device on a single chip is rapidly growing to meet this demand but the ability of two dimensional layouts in circuit design and fabrication to accommodate these demands has reached its limits.
Recently, three-dimensional integrated circuits (3D-ICs) have been providing breakthroughs to this bottleneck. A 3D-IC is a chip in which two or more layers of active electronic components are integrated both vertically and horizontally into a single integrated circuit. This is also referred to as three-dimensional stacking. 3-D wafer stacking represents a wafer level packaging technique in which specific components, such as logic, memory, sensors, A/D converters, controllers, etc., are fabricated on separate wafer platforms and then integrated onto a single wafer-scale or chip-scale package using Through-Silicon Vias (TSVs) to provide the electrical interconnection between the components in the 3-D stack. It provides various advantages such as higher integration, better system performance, lower parasitic losses, and less power consumption. Consequently, many chip designers and manufacturers have shifted to this novel technique.
One of the critical processes for realizing 3D-IC is the fabrication of TSVs. Several techniques have been reported while electrodeposition—the depositing of metal into vias through electroplating process—is frequently applied. Different conductive materials like copper, gold, polysilicon, and tin have been adopted but copper is mostly chosen due to its better electrical conductivity and electromigration resistance.
TSVs have been widely used for forming electrical connections between corresponding layers in stacked or 3D arrangements in devices like memory, MEMS, radio frequency chip, and other semiconductor devices. Nevertheless, vias can easily suffer from defects caused, at least partially, by electroplating pure or near pure metal into the high aspect ratio vias distributed throughout a wafer. The commonly found defects include internal stresses in the metal deposit, non-uniform deposits, inclusions of gases, and excess metal deposition at the inlet and outlet of vias. Severe adverse effects are produced in devices fabricated with these defects.
In general, there are many factors dictating the quality of vias including plating bath or equipment used, via geometry, and additives used. The concentration and type of additives, via shape, aspect ratio (depth/width), and current loading are frequently studied so as to optimize the electrodeposition performance in such complex process. A traditional approach of investigating the abovementioned parameters is through experiments. Experiments can provide solid results but a large number of experiments are usually required. For example, if there are six process parameters to be studied and adjusted in the process, it may induce more than several hundreds of experiments because of the possible permutations of parameters, following by a large of amount of time and cost.
For solving the abovementioned problems, computer simulation is deployed to simulate the electroplating process for determining the suitable process window of process parameters. For example, U.S. Pat. No. 7,279,084 discloses an electroplating method, which uses a computer to generate a model for calculating the current ratio between an inner anode and outer anode. For another example, U.S. Pat. No. 7,544,280 teaches a plating analyzing method for analyzing an electroplating system having an anode, a cathode and plating liquid, based on a Laplace equation discrete by finite volume method for calculating potential distribution. U.S. Pat. No. 7,189,318 also discloses a facility for configuring the electrical parameters in accordance with mathematical model of a processing chamber that corrects for any deficiencies measured during processing.
However, the above prior arts mainly focus on the current and potential used in the electroplating process regarding the wafer plating uniformity but fail to consider via geometry such as via diameter and aspect ratio. Accurate simulation can hardly be achieved without detailed consideration about the geometrical properties of vias and their distribution on wafer. And in general, the accuracy of the computer simulation method as compared against the reality is always a major concern. As a common practice, more consideration factors and more detailed models can be used to enhance the realism of a computer simulation. Nevertheless, the time and computing resources needed for running such computer simulation will increase enormously at the same time, especially given the wafers in the recent years are getting larger and larger in size and the semiconductor devices are being more and more integrated.
Consequently, there is an urgent need to provide a method for optimizing an electrodeposition process of vias through computer simulation with high accuracy while keeping simulation time as short as possible.